This invention relates to noise reduction circuits, for example noise reduction circuits which are useful in clock restoration circuits.
The invention also finds application, inter alia, in fractional rate multiplier circuits and in fractional-N frequency synthesisers.
Computing and telecommunications systems operate with internal or external clock signals which effect modulation, demodulation, analogue-to-digital conversion and synchronisation of data streams. A high level of purity and/or integrity is often required by system clocks. By purity is meant low phase noise, directly proportional to time jitter. Phase noise or time jitter arises when the position of a pulse in a pulse train is displaced in time from the position expected on the assumption of strict periodicity of the pulse train. By integrity is meant a pulse stream in which none of the operative transitions is missing and in which there are no spurious, additional transitions.
A known phase-noise reduction or anti-jitter circuit is described in PCT/GB97/00405 (Publication No. WO97/30516). This circuit produces an output whose frequency is the same as the input, but whose output pulses have reduced jitter compared to the input pulses.
Noise reduction circuits according to the present invention can be used to reduce noise caused by low-level purity and/or integrity. Circuits according to the invention find a range of different applications; for example, as clock restoration circuits, in multiphase output clock distribution circuits, in low noise fractional rate multiplier circuits and in fractional-N phase locked loop synthesisers.
According to a first aspect of the invention there is provided a noise reduction circuit for reducing noise in an input pulse train consisting of pulses which in the absence of noise are periodic and from which one or more pulses is missing, the noise reduction circuit including DC removal means for removing a DC level from the input pulse train, integrator means for integrating the input pulse train after a DC level has been removed therefrom by the DC removal means, detection means for receiving an output from the integrator means and detecting therefrom a missing pulse in the input pulse train, pulse generating means responsive to the detection means for inserting into the input pulse train an additional pulse delayed with respect to a missing pulse detected by the detection means and output means for deriving an output pulse train from said output from the integrator means.
According to a second aspect of the invention there is provided a voltage controlled oscillator comprising a voltage source for generating a presettable voltage, integrator means having an input for receiving the presettable voltage, means for supplying pulses to said input in response to an output from the integrator means and means for deriving from said output a periodic pulse train at a frequency determined by the presentable voltage.
According to a third aspect of the invention there is provided a frequency multiplier comprising integrator means having an input for receiving an input pulse train having a nominal frequency f, a voltage source for supplying a presettable voltage to said input, means for inserting additional pulses into said input pulse train in response to an output from the integrator means and means for deriving from said output a periodic pulse train at a frequency nf, where n is a multiple greater than unity determined by said presettable voltage.
According to a fourth aspect of the invention there is provided a phase noise reduction circuit for reducing phase noise in an input pulse train consisting of pulses which in the absence of phase noise have a nominal frequency f, the phase noise reduction circuit comprising means for deriving a first pulse train from the input pulse train, the first pulse train consisting of pulses triggered by the positive-going transitions of the pulses forming the input pulse train, means for deriving a second pulse train from the input pulse train, the second pulse train consisting of pulses triggered by the negative-going transitions of the pulses forming the input pulse train, combining means for combining said first and second pulse trains to form a combined pulse train, DC removal means for removing a DC level for the combined pulse train, integrating means for integrating the combined pulse train after a DC level has been removed therefrom by the DC removal means to produce an integrated output and processing means for deriving from the integrated output an output pulse train at said nominal frequency f.
According to a fifth aspect of the invention there is provided a circuit for reducing noise in an input pulse train consisting of pulses which are periodic in the absence of noise and amongst which one or more spurious additional pulse is present, the circuit including DC removal means for removing a DC level from the input pulse train, integrator means for integrating the input pulse train after a DC level has been removed therefrom by the DC removal means, pulse deletion means for deleting a said spurious additional pulse from the input pulse train and output means for deriving an output pulse train from an output of the integrator means.
According to a sixth aspect of the invention there is provided a circuit for reducing phase noise in an input pulse train consisting of pulses which are periodic in the absence of noise, the circuit including DC removal means for removing a DC level from the input pulse train, integrator means for integrating the input pulse train after a DC level has been removed therefrom by the DC removal means and at least two detection means for producing different output pulse trains in response to an output of the integrator means and to respectively different reference signals, whereby each said output pulse train contains periodic transitions having a phase relationship to the input pulse train dependent on the corresponding reference signal.
According to a seventh aspect of the invention there is provided a fractional rate multiplier circuit comprising pulse train modification means for subtracting a pulse from or adding a pulse to an input pulse train in response to a control pulse to produce a modified pulse train, divider means for dividing the modified pulse train by a presettable integer, a fractional rate multiplier for deriving control pulses from the divider output and supplying the control pulses to the pulse train modification means and jitter reducing means for reducing jitter in the modified pulse train prior to division thereof by the divider means.
According to an eighth aspect of the invention there is provided a fractional-N frequency synthesiser comprising a phase-locked loop containing a fractional rate multiplier circuit according to the seventh aspect of the invention.